High-speed interfaces and associated transmitters and corresponding differential receivers suitable for high-speed data transfers are known. High speed requires precisely adjusted transmitters and receivers to provide reliable data transfer. To increase data transfer rates and run interfaces at higher speeds, it becomes more difficult to provide a clean signal and as such the driver strength needs to be controlled to improve signal to noise levels and signal integrity. For example, a double data rate (DDR2) memory interface has a type of Off-Chip Driver calibration mechanism (OCD—Off-Chip Driver calibration) to allow for a transmitter on the memory side to be calibrated and programmed to a suitable strength level, by a memory controller connected on the other side of interface.
FIG. 1 shows conventional DDR2 memory interface. In this example, DDR memory 10, an integrated circuit chip, communicates with a memory controller of another integrated circuit chip 12 via bi-directional data bus 14 and unidirectional command bus 40. Each end of the data bus 14 includes programmable strength transmitters 16 and 18, differential receivers 20 and 22, and programmable termination resistor arrays 24 and 26, as part of an input/output (IO) circuit.
In addition, each of the differential receivers 20 and 22 is coupled to a precision resistor divider, typically external to the respective chips 10 and 12, which provides a precision reference voltage for the receivers. The voltage reference sources 30 and 32, as noted, are each typically made out of two external precision resistors that are mounted on printed circuit board or other substrate.
Typical “read” data transfer from memory 10 to controller 12 goes as follows: Controller 12 sends a request for “read” data transfer to memory 10; Controller 12 enables termination via termination resistor array 24 on data bus 14 in order to condition incoming data for reliable receiving; Memory 10 sends data via data bus 14 to controller 12; Controller 12's receiver 22 compares the signal level of incoming data with reference voltage VREF; Based on the comparison result, over/under VREF, data 1 or 0 are presented to controller 12. In order to avoid false transfer and misdetection on the receiving side, data are required to be not just over or under the reference voltage, but to be over or under with a specified margin level.
With the DDR2 configuration there is an option of an off-chip driver calibration technique that allows a memory controller 12 to check the level of a signal driven by memory 10 and to tell the memory chip 10 to adjust its transmitter 16, change driver strength and consequently change the signal level. Memory transmitter 16 has its driver strength programmable in a number of steps, typically sixteen steps. The driver strength of memory controller transmitter 18 is usually adjusted by the memory controller's own impedance controller, typically in sixteen steps. The usual way to calibrate the memory driver 16 by the memory controller using 12 the Off-Chip Driver calibration mechanism is to first calibrate the memory controller's own driver 18 to a required impedance using the memory controller's own impedance calibration circuit and external reference resistor and then match the memory driver 16 by turning on both the memory driver 16 and the controller driver 18 at the same time driving opposite signal values on bi-directional data bus 14 and comparing resulting signal levels with the reference voltage 30 by the controller's own receiver 22, and accordingly instruct memory via command bus 40 to increase or decrease the transmitter 16 driver strength.
However, this method does not do calibration at nominal operating conditions when termination 24 is turned on and non-active transmitter 18 is turned off. In addition, this method does not provide information about level margins about the reference voltage. So, for this kind of calibration to work reliably, to provide the necessary margin levels for reliable data transfer, it is necessary to know and account for transmitters strength curves (voltage-current), both for memory transmitter 16 being calibrated and controller transmitter 18 used as the reference. As such, calibration done with the fixed VREF reference voltage provided by the precision resistors that are off-chip, do not allow the detection of how marginal a signal level truly may be. With the described calibration method, relying on transmitter 18 in the receiving side controller 12 to provide the reference for calibrating transmitter 16 on the transmitting side memory 10 can be applied only to the bi-directional bus, bus that has transmitters on both sides.
Therefore, there exists a need to address one or more of the above noted problems.